Number of commits found: 8
Commit History - (may be incomplete: for full details, see links to repositories near top of page) |
Commit | Credits | Log message |
g20220920 09 Oct 2022 19:02:15 |
Yuri Victorovich (yuri) Author: Emmanuel Vadot |
cad/abc: Update g20200322 -> g20220920
PR: 266917 260806
Approved by: uddka@student.kit.edu (maintainer's timeout; 9+ months on
PR#260806) |
07 Sep 2022 21:58:51 |
Stefan Eßer (se) |
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner) |
g20200322 07 Sep 2022 21:10:59 |
Stefan Eßer (se) |
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above ) |
g20200322 07 Apr 2021 08:09:01 |
Mathieu Arnold (mat) |
One more small cleanup, forgotten yesterday.
Reported by: lwhsu |
g20200322 06 Apr 2021 14:31:07 |
Mathieu Arnold (mat) |
Remove # $FreeBSD$ from Makefiles. |
g20200322 22 Mar 2020 08:56:59 |
yuri |
cad/abc: Update g20180420 -> g20200322
PR: 241511
Approved by: uddka@student.kit.edu (maintainer's timeout; 4.5 months) |
g20180420_1 09 Apr 2019 14:04:50 |
sunpoet |
Update devel/readline to 8.0
- Bump PORTREVISION of dependent ports for shlib change
Changes: https://tiswww.case.edu/php/chet/readline/CHANGES
PR: 236156
Exp-run by: antoine |
g20180420 24 Apr 2018 07:53:29 |
yuri |
New port: cad/abc: System for sequential synthesis and verification
PR: 227254
Submitted by: Christian Kramer <uddka@student.kit.edu> |
Number of commits found: 8
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