ChipVault is a VHDL and Verilog Chip Design Organization tool which improves
design efficiency by:
- Providing the ability to Navigate and Edit files Hierarchically.
- Automatically generating Schematic Component Port views of VHDL and
Verilog RTL files.
- Automating RTL instantiation and template generation.
- Providing Revision Control (designed for HW, not SW development).
- Supporting External Tool Hooks (bottom-up vcoms,etc).
- Providing an Issue Tracking Log with sorting.
- Providing Netlist sorting and hierarchy viewing.
- Supporting web-sharing of RTL files (both encrypted and clear).
- Fast and Nimble.
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above )
