| Port details |
- gplcver Verilog HDL simulator
- 2.12.a cad
 =2      2.12.aVersion of this port present on the latest quarterly branch. - There is no maintainer for this port.
- Any concerns regarding this port should be directed to the FreeBSD Ports mailing list via ports@FreeBSD.org
- Port Added: 2005-12-29 03:53:04
- Last Update: 2024-10-28 12:42:03
- Commit Hash: 00fb86f
- People watching this port, also watch:: jdictionary, py311-Automat, py311-python-gdsii, py39-PyOpenGL, p5-Sane
- License: GPLv2
- WWW:
- https://sourceforge.net/projects/gplcver/
- Description:
- GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
implements some of the 2001 P1364 standard features including all three
PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
Reference Manual (LRM).
Verilog is the name for both a language for describing electronic hardware
called a hardware description language (HDL) and the name of the program
that simulates HDL circuit descriptions to verify that described circuits
will function correctly when the are constructed. Verilog is used only for
describing digital logic circuits. Other HDLs such as Spice are used for
describing analog circuits. There is an IEEE standard named P1364 that
standardizes the Verilog HDL and the behavior of Verilog simulators.
Verilog is officially defined in the IEEE P1364 Language Reference
Manual (LRM) that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach digital circuit
design using Verilog.
  ¦  ¦  ¦  ¦ 
- Manual pages:
- FreshPorts has no man page information for this port.
- pkg-plist: as obtained via:
make generate-plist - Dependency lines:
-
- To install the port:
- cd /usr/ports/cad/gplcver/ && make install clean
- To add the package, run one of these commands:
- pkg install cad/gplcver
- pkg install gplcver
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.- PKGNAME: gplcver
- Flavors: there is no flavor information for this port.
- distinfo:
- SHA256 (gplcver-2.12a.src.tar.bz2) = f7d94677677f10c2d1e366eda2d01a652ef5f30d167660905c100f52f1a46e75
SIZE (gplcver-2.12a.src.tar.bz2) = 1224470
Packages (timestamps in pop-ups are UTC):
- Dependencies
- NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
- Build dependencies:
-
- gmake>=4.4.1 : devel/gmake
- There are no ports dependent upon this port
Configuration Options:- ===> The following configuration options are available for gplcver-2.12.a:
DOCS=on: Build and/or install documentation
===> Use 'make config' to modify these settings
- Options name:
- cad_gplcver
- USES:
- tar:bzip2 gmake
- FreshPorts was unable to extract/find any pkg message
- Master Sites:
|
| Commit History - (may be incomplete: for full details, see links to repositories near top of page) |
| Commit | Credits | Log message |
|---|
2.12.a
28 Oct 2024 12:42:03
 |
Robert Clausecker (fuz) |
cad/gplcver: fix build on recent FreeBSD
The option -export-dynamic is a linker option not (no longer?)
understood by the compiler; pass -rdynamic to the compiler to have it
pass -export-dynamic to the linker instead. |
07 Sep 2022 21:58:51
|
Stefan Eßer (se) |
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner) |
2.12.a
07 Sep 2022 21:10:59
|
Stefan Eßer (se) |
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above  ) |
2.12.a
20 Jul 2022 14:20:58
|
Tobias C. Berner (tcberner) |
cad: remove 'Created by' lines
A big Thank You to the original contributors of these ports:
* AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
* Alexey Dokuchaev <danfe@FreeBSD.org>
* Anders Andersson <anders@hack.org>
* Bruce M Simpson <bms@FreeBSD.org>
* Christoph Moench-Tegeder <cmt@FreeBSD.org>
* David Yeske <dyeske@gmail.com>
* Diane Bruce <db@db.net>
* Joachim Strombergson <watchman@ludd.ltu.se>
* Johnny Sorocil <jsorocil@gmail.com>
* Julian Jenkins <kaveman@magna.com.au>
* Marc Fonvieille <blackend@FreeBSD.org> (Only the first 15 lines of the commit message are shown above ) |
2.12.a
06 Apr 2021 14:31:07
|
Mathieu Arnold (mat) |
Remove # $FreeBSD$ from Makefiles. |
2.12.a
19 Jun 2019 10:16:48
 |
danfe |
- Fix the checks to avoid using `sys/dir.h' and thus undeprecate
- Define LICENSE (GPLv2) and install supplied documentation files |
2.12.a
12 Jun 2019 06:52:51
|
bapt |
Mark as deprecated a bunch of abandonware using sys/dir.h
sys/dir.h is going to be phased out soon, so mark as deprecated non maintained
abandonware using it.
PR: 21519 |
2.12.a
20 Jan 2017 20:33:31
|
sunpoet |
Update WWW: SF redirects to https://sourceforge.net/projects/<PROJECT_NAME>/ |
2.12.a
09 Jun 2014 11:21:53
|
olgeni |
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.
CR: D196
Approved by: portmgr (bapt) |
2.12.a
01 Jun 2014 14:48:08
|
ohauer |
- USE_(BZIP2|XZ) -> USES=tar:(bzip2|xz) |
2.12.a
27 Feb 2014 13:43:28
|
ehaupt |
Support staging |
2.12.a
20 Sep 2013 15:58:42
|
bapt |
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad) |
2.12.a
16 Jun 2011 10:41:31
|
bapt |
Point to the new home
Make it fetchable again |
2.12.a
20 Mar 2011 12:54:45
|
miwi |
- Get Rid MD5 support |
2.12.a
27 Oct 2008 15:59:27
|
tabthorpe |
- Reassign to ports |
2.12.a
23 Aug 2007 04:00:04
|
tabthorpe |
- change maintainer address on ports I maintain
Approved by: clsung (mentor) |
2.12.a
21 Jul 2007 01:21:52
|
ijliao |
'actually' pass maintainership |
2.12.a
21 Jul 2007 01:20:50
|
ijliao |
upgrade to 2.12.a
pass maintainership to submitter
PR: 114768
Submitted by: Thomas Abthorpe <thomas@goodking.ca> |
2.11.a
03 Aug 2006 03:26:38
|
clsung |
- maintainer is a committer |
2.11.a
20 Jan 2006 14:18:34
|
arved |
Fix build on sparc |
2.11.a
19 Jan 2006 23:31:12
|
kris |
BROKEN on sparc64: Does not compile |
2.11.a
04 Jan 2006 05:56:54
|
edwin |
Fix maintainership (set to submitter) |
2.11.a
29 Dec 2005 03:48:58
|
edwin |
[NEW PORT] cad/gplcver: A Verilog HDL simulator
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw> |
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