| Port details |
- sis Synthesis program for the synthesis of sequential circuits
- 1.2.1 cad
 =3      1.2.1Version of this port present on the latest quarterly branch.  BROKEN: "Does not compile"
- Maintainer: volf@oasis.IAEhv.nl
- Port Added: unknown
- Last Update: 2003-08-08 03:33:42
- SVN Revision: UNKNOWN
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- License: not specified in port
- Description:
- sis is an interactive program for the synthesis of both synchronous
and asynchronous sequential circuits. The input can be given in state
table format or as logical equations (for synchronous circuits), or
as a signal transition graph (for asynchronous circuits); a target
technology library is given in genlib format. The output is a netlist
of gates in the target technology.
The system includes various capabilities that are controlled interactively
by the user. These include state minimization, state assignment,
optimization for area and delay using retiming, optimization using
standard algebraic and Boolean combinational techniques from MISII,
performance optimization using restructuring, and technology mapping
for optimal area and delay. Redundancy removal and 100% testability
are provided for combinational and scan-path circuits. Formal verification
is available for both combinational and sequential circuits, even for
circuits with different state encodings.
This distribution contains sis, nova (state assignment), jedi (state
assignment), stamina (state minimization, from June Rho at University of
Colorado, Boulder), sred (state minimization), espresso, blif2vst (mapped
BLIF to structural VHDL translator), vst2blif (structural VHDL to BLIF
translator), xsis (a front-end graphical interface to sis) and several stripped
down packages from the OctTools (options, port, and utility) that are needed
for some of the programs listed above.
Frank Volf, volf@oasis.IAEhv.nl
cgit ¦ GitHub ¦ GitHub ¦ GitLab ¦ 
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- Master Sites:
|
| Commit History - (may be incomplete: for full details, see links to repositories near top of page) |
| Commit | Credits | Log message |
|---|
1.2.1
08 Aug 2003 03:33:42
  |
kris |
As announced on May 6, remove the broken sis port. |
1.2.1
06 May 2003 23:51:09
|
kris |
BROKEN: Does not compile |
1.2.1
21 Feb 2003 11:04:55
|
knu |
De-pkg-comment. |
14 Feb 2001 05:43:01
    |
lioux |
typo clean up police: \s -> \t |
12 Jan 2001 17:15:14
|
alex |
Use the correct path in the $(TAR) command |
08 Oct 2000 00:25:37
|
asami |
Convert category cad to new layout. |
16 Sep 2000 19:40:55
|
ade |
Support CC/CFLAGS/PREFIX/X11BASE/MAKE properly Sort pkg/PLIST |
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