Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog
Object Model with VPI Interface, Elaborator, Serialization, Visitor and
Listener. Used as a compiled interchange format in between SystemVerilog tools.
libuhdm implements the hardware object model standardized in:
IEEE 1800.1-2017 chapter 37: VPI object model.
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above )
Update CONFLICTS definitions in categories a* to c*
Update the CONFLICTS definitions of ports in the following categories:
- accessibility
- archivers
- audio
- benchmarks
- biology
- cad
- chinese
- comms
- converters
An attempt has been made to use generic conflicts patterns that do not
have to be updated whenever a new version of a conflicting port is
added to the ports system.
There is a misunderstanding that the port being built/installed has to
be omitted from the conflicts pattern. This is not true - the port
being built is implicitly non-conflicting due to logic in bsd.port.mk.
Approved by: portmgr (implicit)
