| Port details |
- riscv-isa-sim Spike, a RISC-V ISA Simulator
- 1.1.0.20240531 emulators
 =2      1.1.0.20240531Version of this port present on the latest quarterly branch. - Maintainer: lwhsu@FreeBSD.org
- Port Added: 2017-02-07 15:33:13
- Last Update: 2024-06-08 07:32:36
- Commit Hash: 659ccd0
- People watching this port, also watch:: jdictionary, py311-Automat, py311-python-gdsii, py39-PyOpenGL, p5-Sane
- License: BSD3CLAUSE
- WWW:
- https://github.com/riscv/riscv-isa-sim
- Description:
- Spike, a RISC-V ISA Simulator
The RISC-V ISA Simulator implements a functional model of one or more RISC-V
processors.
  ¦  ¦  ¦  ¦ 
- Manual pages:
- FreshPorts has no man page information for this port.
- pkg-plist: as obtained via:
make generate-plist - Dependency lines:
-
- riscv-isa-sim>0:emulators/riscv-isa-sim
- To install the port:
- cd /usr/ports/emulators/riscv-isa-sim/ && make install clean
- To add the package, run one of these commands:
- pkg install emulators/riscv-isa-sim
- pkg install riscv-isa-sim
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.- PKGNAME: riscv-isa-sim
- Flavors: there is no flavor information for this port.
- NOT_FOR_ARCHS: i386
- distinfo:
- TIMESTAMP = 1717831105
SHA256 (riscv-riscv-isa-sim-1.1.0-20240531-00dfa28_GH0.tar.gz) = 5489098fd67d2d8cfbc714a6e93464ca702125ab0308a523de8528f474a5c80d
SIZE (riscv-riscv-isa-sim-1.1.0-20240531-00dfa28_GH0.tar.gz) = 492848
Packages (timestamps in pop-ups are UTC):
- Dependencies
- NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
- Build dependencies:
-
- gmake>=4.4.1 : devel/gmake
- There are no ports dependent upon this port
Configuration Options:- No options to configure
- Options name:
- emulators_riscv-isa-sim
- USES:
- compiler:c++11-lang gmake shebangfix
- FreshPorts was unable to extract/find any pkg message
- Master Sites:
|
| Commit History - (may be incomplete: for full details, see links to repositories near top of page) |
| Commit | Credits | Log message |
|---|
1.1.0.20240531
08 Jun 2024 07:32:36
 |
Li-Wen Hsu (lwhsu)
Author: SHENG-YI HONG |
emulators/riscv-isa-sim: Update to 2024-05-31 snapshot
Reviewed by: mhorne
Event: Kitchener-Waterloo Hackathon 202406
Differential Revision: https://reviews.freebsd.org/D43251 |
07 Sep 2022 21:58:51
|
Stefan Eßer (se) |
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner) |
g_20211015
07 Sep 2022 21:10:59
|
Stefan Eßer (se) |
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above  ) |
g_20211015
19 Oct 2021 02:31:22
|
Li-Wen Hsu (lwhsu) |
emulators/riscv-isa-sim: Update to 20211015 snapshot
While here, switch to NOT_FOR_ARCHS because it builds at least on
aarch64, armv7 and we need to test other arches more. [1]
Reported by: Robert Clausecker <fuz@fuz.su> [1] |
g_20201102
07 Apr 2021 08:09:01
|
Mathieu Arnold (mat) |
One more small cleanup, forgotten yesterday.
Reported by: lwhsu |
g_20201102
06 Apr 2021 14:31:07
|
Mathieu Arnold (mat) |
Remove # $FreeBSD$ from Makefiles. |
g_20201102
28 Jan 2021 15:33:10
 |
pkubaj |
emulators/riscv-isa-sim: enable on powerpc64 |
g_20201102
26 Jan 2021 13:16:54
|
pkubaj |
emulators/riscv-isa-sim: enable on powerpc64le |
g_20201102
09 Nov 2020 13:45:01
|
mhorne |
Update riscv-isa-sim to 2020-11-02 snapshot
- Switch to the official upstream, github.com/riscv/riscv-isa-sim.
- Remove emulators/riscv-fesvr, as it is now bundled with Spike.
- Drop patches.
Submitted by: lwhsu (earlier version)
Reviewed by: lwhsu
Approved by: lwhsu (ports, maintainer)
Differential Revision: https://reviews.freebsd.org/D27144 |
g_20181007
26 Jul 2019 20:46:57
|
gerald |
Bump PORTREVISION for ports depending on the canonical version of GCC
as defined in Mk/bsd.default-versions.mk which has moved from GCC 8.3
to GCC 9.1 under most circumstances now after revision 507371.
This includes ports
- with USE_GCC=yes or USE_GCC=any,
- with USES=fortran,
- using Mk/bsd.octave.mk which in turn features USES=fortran, and
- with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, everything INDEX-11 shows with a dependency on lang/gcc9 now.
PR: 238330 |
g_20181006
12 Dec 2018 01:35:36
|
gerald |
Bump PORTREVISION for ports depending on the canonical version of GCC
defined via Mk/bsd.default-versions.mk which has moved from GCC 7.4 t
GCC 8.2 under most circumstances.
This includes ports
- with USE_GCC=yes or USE_GCC=any,
- with USES=fortran,
- using Mk/bsd.octave.mk which in turn features USES=fortran, and
- with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, as a double check, everything INDEX-11 showed depending on lang/gcc7.
PR: 231590 |
g_20181005
05 Oct 2018 11:07:13
|
lwhsu |
- Update to 20181005 snapshot
Sponsored by: The FreeBSD Foundation |
g_20180104
29 Jul 2018 22:18:46
|
gerald |
Bump PORTREVISION for ports depending on the canonical version of GCC
in the ports tree (via Mk/bsd.default-versions.mk and lang/gcc) which
has now moved from GCC 6 to GCC 7 by default.
This includes ports
- featuring USE_GCC=yes or USE_GCC=any,
- featuring USES=fortran,
- using Mk/bsd.octave.mk which in turn features USES=fortran, and those
- with USES=compiler specifying one of openmp, nestedfct, c11, c++0x,
c++11-lib, c++11-lang, c++14-lang, c++17-lang, or gcc-c++11-lib.
PR: 222542 |
g_20180103
07 Jan 2018 16:34:57
|
lwhsu |
- Update to 20180103 snapshot |
g_20170810
10 Sep 2017 20:55:39
|
gerald |
Bump PORTREVISION for ports depending on the canonical version of GCC
(via Mk/bsd.default-versions.mk and lang/gcc) which has moved from
GCC 5.4 to GCC 6.4 under most circumstances.
This includes ports
- with USE_GCC=yes or USE_GCC=any,
- with USES=fortran,
- using Mk/bsd.octave.mk which in turn features USES=fortran, and
- with USES=compiler specifying openmp, nestedfct, c++11-lib, c++11-lang,
c++14-lang, c++0x, c11, or gcc-c++11-lib.
PR: 219275 |
g_20170809
11 Aug 2017 17:50:49
|
lwhsu |
- Update to 20170809 snapshot |
g_20170207
01 Apr 2017 15:23:32
|
gerald |
Bump PORTREVISIONs for ports depending on the canonical version of GCC and
lang/gcc which have moved from GCC 4.9.4 to GCC 5.4 (at least under some
circumstances such as versions of FreeBSD or platforms).
This includes ports
- with USE_GCC=yes or USE_GCC=any,
- with USES=fortran,
- using using Mk/bsd.octave.mk which in turn has USES=fortran, and
- with USES=compiler specifying openmp, nestedfct, c++11-lib, c++14-lang,
c++11-lang, c++0x, c11, or gcc-c++11-lib.
PR: 216707 |
g_20170206
08 Feb 2017 07:08:25
|
lwhsu |
- Makr only for amd64 |
g_20170206
07 Feb 2017 15:33:04
|
lwhsu |
Add RISC-V ISA Simulator:
- emulators/riscv-fesvr, RISC-V Frontend Server
- emulators/riscv-isa-sim, Spike, a RISC-V ISA Simulator
Original work is done by sbruno
Reviewed by: br (earlier version)
Differential Revision: https://reviews.freebsd.org/D7527 |
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