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Port details
yosys-systemverilog SystemVerilog support for Yosys
2023.06.14 cad on this many watch lists=3 search for ports that depend on this port Find issues related to this port Report an issue related to this port View this port on Repology. pkg-fallout 2023.06.14Version of this port present on the latest quarterly branch.
Broken BROKEN: incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845
Ignore IGNORE: is marked as broken: incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845
Maintainer: yuri@FreeBSD.org search for ports maintained by this maintainer
Port Added: 2023-06-06 21:12:21
Last Update: 2023-07-29 06:39:15
Commit Hash: 3a3bcea
People watching this port, also watch:: supercollider, nim, py311-clang, PrusaSlicer, py311-logzero
License: APACHE20
WWW:
https://github.com/antmicro/yosys-systemverilog
Description:
yosys-systemverilog is a YoSys add-on that contains all moving parts needed to get SystemVerilog support enabled in Yosys.
Homepage    cgit ¦ Codeberg ¦ GitHub ¦ GitLab ¦ SVNWeb - no subversion history for this port

Manual pages:
FreshPorts has no man page information for this port.
pkg-plist: as obtained via: make generate-plist
Expand this list (58 items)
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  1. /usr/local/share/licenses/yosys-systemverilog-2023.06.14/catalog.mk
  2. /usr/local/share/licenses/yosys-systemverilog-2023.06.14/LICENSE
  3. /usr/local/share/licenses/yosys-systemverilog-2023.06.14/APACHE20
  4. bin/sv2v
  5. share/yosys/nexus/dsp_rules.txt
  6. share/yosys/plugins/design_introspection.so
  7. share/yosys/plugins/dsp-ff.so
  8. share/yosys/plugins/fasm.so
  9. share/yosys/plugins/fasm_extra_modules/BANK.v
  10. share/yosys/plugins/integrateinv.so
  11. share/yosys/plugins/params.so
  12. share/yosys/plugins/ql-iob.so
  13. share/yosys/plugins/ql-qlf.so
  14. share/yosys/plugins/sdc.so
  15. share/yosys/plugins/systemverilog.so
  16. share/yosys/plugins/uhdm.so
  17. share/yosys/plugins/xdc.so
  18. share/yosys/quicklogic/pp3/abc9_map.v
  19. share/yosys/quicklogic/pp3/abc9_model.v
  20. share/yosys/quicklogic/pp3/abc9_unmap.v
  21. share/yosys/quicklogic/pp3/bram_init_32.vh
  22. share/yosys/quicklogic/pp3/bram_init_8_16.vh
  23. share/yosys/quicklogic/pp3/brams.txt
  24. share/yosys/quicklogic/pp3/brams_map.v
  25. share/yosys/quicklogic/pp3/brams_sim.v
  26. share/yosys/quicklogic/pp3/cells_map.v
  27. share/yosys/quicklogic/pp3/cells_sim.v
  28. share/yosys/quicklogic/pp3/ffs_map.v
  29. share/yosys/quicklogic/pp3/latches_map.v
  30. share/yosys/quicklogic/pp3/lut_map.v
  31. share/yosys/quicklogic/pp3/lutdefs.txt
  32. share/yosys/quicklogic/pp3/mult_sim.v
  33. share/yosys/quicklogic/pp3/qlal3_sim.v
  34. share/yosys/quicklogic/pp3/qlal4s3b_sim.v
  35. share/yosys/quicklogic/qlf_k6n10/arith_map.v
  36. share/yosys/quicklogic/qlf_k6n10/brams.txt
  37. share/yosys/quicklogic/qlf_k6n10/brams_map.v
  38. share/yosys/quicklogic/qlf_k6n10/cells_sim.v
  39. share/yosys/quicklogic/qlf_k6n10/dsp_map.v
  40. share/yosys/quicklogic/qlf_k6n10/ffs_map.v
  41. share/yosys/quicklogic/qlf_k6n10/lut_map.v
  42. share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
  43. share/yosys/quicklogic/qlf_k6n10f/arith_map.v
  44. share/yosys/quicklogic/qlf_k6n10f/brams.txt
  45. share/yosys/quicklogic/qlf_k6n10f/brams_final_map.v
  46. share/yosys/quicklogic/qlf_k6n10f/brams_map.v
  47. share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
  48. share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
  49. share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
  50. share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
  51. share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
  52. share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
  53. share/yosys/quicklogic/qlf_k6n10f/primitives_sim.v
  54. share/yosys/quicklogic/qlf_k6n10f/sram1024x18.v
  55. share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
  56. @owner
  57. @group
  58. @mode
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Dependency lines:
  • yosys-systemverilog>0:cad/yosys-systemverilog
To install the port:
cd /usr/ports/cad/yosys-systemverilog/ && make install clean
We doubt a package is available for this port because we see it marked as as:
  • Broken
  • Ignore
Packages are normally not provided for ports that are marked as above.
To add the package, run one of these commands:
  • pkg install cad/yosys-systemverilog
  • pkg install yosys-systemverilog
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.
PKGNAME: yosys-systemverilog
Flavors: there is no flavor information for this port.
distinfo:
TIMESTAMP = 1687103884 SHA256 (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 810f8e85ea6b87c37cba10f7660d7f1aa0ba251c1275e3a18c312964bb329a63 SIZE (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 86004

Expand this list (32 items)

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SHA256 (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = b8b12e7f8795cf13037bb062d453b86c788eae62558586f59e9419aabe6e9bef SIZE (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = 65154 SHA256 (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = fcba79b60ef87bdd4976332e998589a62e1be012b932b543b49de5e0620eef1b SIZE (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = 7617 SHA256 (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 8b4e7dc5a6c5fd666f8f7163232931ab28746d0d17da8fa1cbd68be9e878881b SIZE (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 183409 SHA256 (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 1b4000ea82b81f69d46d0af4152c10c6303873510738e24cfc4767760d30e3f8 SIZE (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 25094 SHA256 (cabal/hashable-1.4.2.0/revision/1.cabal) = 585792335d5541dba78fa8dfcb291a89cd5812a281825ff7a44afa296ab5d58a SIZE (cabal/hashable-1.4.2.0/revision/1.cabal) = 4520 SHA256 (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 5553c21b4a789f9b591eed69e598cc58484c274af29250e517b5a8bcc62b995f SIZE (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 57222 SHA256 (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = d8f97ac14ab47b6b8a7b0fdb4ff95426322ec56badd01652ac15da4a44d4bab8 SIZE (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = 14838 SHA256 (cabal/th-compat-0.1.4/revision/2.cabal) = e5ae7c083ef3a22248558f8451669bb1c55ea8090f5908b86b9033743c161730 SIZE (cabal/th-compat-0.1.4/revision/2.cabal) = 3224 SHA256 (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = c5d3167d15e12f52e00879ddf304a591672a74e369cc47bc5c7fa1d5a8d15b4f SIZE (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = 154509 SHA256 (cabal/vector-0.13.0.0/revision/3.cabal) = fa5cac81a17a5af388716792e8b99c24b3b66770086756d0d8b23f8272a0244c SIZE (cabal/vector-0.13.0.0/revision/3.cabal) = 9112 SHA256 (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = a888210f6467f155090653734be5cc920406a07227e0d3adb59096716fdb806c SIZE (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = 12377 SHA256 (cabal/vector-stream-0.1.0.0/revision/2.cabal) = f5d6d5291cd1b5f2f063403593f1f5c8127d692c888eedeb3e1eb40497a88dca SIZE (cabal/vector-stream-0.1.0.0/revision/2.cabal) = 1404 SHA256 (cabal/antmicro-yosys-systemverilog-2023-06-14-49069fb-2023-06-14_GH0.tar.gz) = 56c4b96f1be7acfee147033d1f726c82b83ee61ccc8dd18e95914f21e3c5e6b6 SIZE (cabal/antmicro-yosys-systemverilog-2023-06-14-49069fb-2023-06-14_GH0.tar.gz) = 157988 SHA256 (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = e2bf0adae00912e07524f2ecf5f6de3d395d283890652d38568175ad56d7bada SIZE (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = 2690136 SHA256 (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = b03955f19128d05c2a2c9d162b2b946fd23a220146abbc5b7847c83c3f937e90 SIZE (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = 279380 SHA256 (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = ad4b43d55d98d2cc6f4892c1af6b0770af994a51f0cf8d450029f2a404738b8a SIZE (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = 2542646

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No package information for this port in our database
Sometimes this happens. Not all ports have packages. Perhaps there is a build error. Check the fallout link: pkg-fallout
Dependencies
NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
Build dependencies:
  1. bash : shells/bash
  2. yosys>0 : cad/yosys
  3. ghc : lang/ghc
  4. cabal : devel/hs-cabal-install
  5. gmake>=4.3 : devel/gmake
  6. pkgconf>=1.3.0_1 : devel/pkgconf
  7. python3.9 : lang/python39
Runtime dependencies:
  1. yosys>0 : cad/yosys
Library dependencies:
  1. libcapnp.so : devel/capnproto
  2. libffi.so : devel/libffi
  3. libsurelog.so : cad/surelog
  4. libuhdm.so : cad/uhdm
  5. libtcmalloc.so : devel/google-perftools
  6. libgmp.so : math/gmp
  7. libffi.so : devel/libffi
  8. libreadline.so.8 : devel/readline
  9. libtcl86.so : lang/tcl86
There are no ports dependent upon this port
Configuration Options:
===> The following configuration options are available for yosys-systemverilog-2023.06.14: TCMALLOC=on: Use the tcmalloc memory allocation library ===> Use 'make config' to modify these settings
Options name:
cad_yosys-systemverilog
USES:
cabal gmake pkgconfig python:build readline tcl
FreshPorts was unable to extract/find any pkg message
Master Sites:
Expand this list (1 items)
Collapse this list.
  1. https://codeload.github.com/antmicro/yosys-systemverilog/tar.gz/49069fb-2023-06-14?dummy=/
Collapse this list.

Number of commits found: 4

Commit History - (may be incomplete: for full details, see links to repositories near top of page)
CommitCreditsLog message
2023.06.14
29 Jul 2023 06:39:15
commit hash: 3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4commit hash: 3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4commit hash: 3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4commit hash: 3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4 files touched by this commit		 Yuri Victorovich (yuri) search for other commits by this committer 
cad/yosys-systemverilog: Broken

Reported by:	fallout
2023.06.14
19 Jun 2023 01:38:52
commit hash: 8914ed49e5ddf883abaa88069e21b204f840f868commit hash: 8914ed49e5ddf883abaa88069e21b204f840f868commit hash: 8914ed49e5ddf883abaa88069e21b204f840f868commit hash: 8914ed49e5ddf883abaa88069e21b204f840f868 files touched by this commit		 Yuri Victorovich (yuri) search for other commits by this committer 
cad/yosys-systemverilog: Add PORTSCOUT tag
2023.06.14
18 Jun 2023 17:10:29
commit hash: c9f634bf9787f8b8586da596316cdbbf8de87b71commit hash: c9f634bf9787f8b8586da596316cdbbf8de87b71commit hash: c9f634bf9787f8b8586da596316cdbbf8de87b71commit hash: c9f634bf9787f8b8586da596316cdbbf8de87b71 files touched by this commit		 Yuri Victorovich (yuri) search for other commits by this committer 
cad/yosys-systemverilog: Update 2023-06-05 → 2023-06-14

Reported by:	portscout
2023.06.05
06 Jun 2023 21:10:58
commit hash: 2fde22d5d05d8c75c5cc93cf98247c837ff43120commit hash: 2fde22d5d05d8c75c5cc93cf98247c837ff43120commit hash: 2fde22d5d05d8c75c5cc93cf98247c837ff43120commit hash: 2fde22d5d05d8c75c5cc93cf98247c837ff43120 files touched by this commit		 Yuri Victorovich (yuri) search for other commits by this committer 
cad/yosys-systemverilog: New port: SystemVerilog support for Yosys

Number of commits found: 4
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